1. Technical Field
The present invention relates generally to computer memories, and in particular, to a system and method for implementing direct cache intervention across semi-private cache memory units. The present invention further relates to processing of castouts in a manner enabling victim caching across same-level cache memories deployed from hierarchically distinct cache memories.
2. Description of the Related Art
A conventional symmetric multiprocessor (SMP) computer system, such as a server computer system, includes multiple processing units all coupled to a system interconnect, which typically comprises one or more address, data and control buses. Coupled to the system interconnect is a system memory, which represents the lowest level of volatile memory in the multiprocessor computer system and which generally is accessible for read and write access by all processing units. In order to reduce access latency to instructions and data residing in the system memory, each processing unit is typically further supported by a respective multi-level cache hierarchy, the lower level(s) of which may be shared by one or more processor cores.
Cache memories are commonly utilized to temporarily store values that might be accessed by a processor in order to speed up processing by reducing access latency introduced by having loading needed values from memory. In some multiprocessor (MP) systems, the cache hierarchy includes at least two levels. The level one (L1), or upper-level cache is usually a private cache associated with a particular processor core and cannot be accessed by other cores in an MP system. The processor core first looks for a data in the upper-level cache. If the requested data is not found in the upper-level cache, the processor core then access lower-level caches (e.g., level two (L2) or level three (L3) caches) for the requested data. The lowest level cache (e.g., L3) is often shared among several processor cores.
At the not fully shared levels of memory, (typically one or more of the upper levels such as L1, L2, and L3 cache levels within a given cache hierarchy), the cache memory is directly accessible by its the processor core and other cache units that are part of the same hierarchy. For upper level cache units outside the given hierarchy and system memory, the given cache is not directly accessible but must instead be accessed by a shared bus transaction in which read and write requests are placed on a shared bus and retrieved and responded to by lower level memory or intervention snooping.
There is a need for a more intelligent system and method for managing a multi-level memory hierarchy to reduce unnecessary memory bus traffic and latency. There is also a need to improve utilization of cache memories included in hierarchies having non-utilized processors.
The present invention addresses these and other needs unresolved by the prior art.